Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs

SRAM-based FPGAs are increasingly relevant in a growing number of safety-critical application fields, ranging from automotive to aerospace. These application fields are characterized by a harsh radiation environment that can cause the occurrence of Single Event Upsets (SEUs) in digital devices. These faults have particularly adverse effects on SRAM-based FPGA systems because not only can they temporarily affect the behaviour of the system by changing the contents of flip-flops or memories, but they can also permanently change the functionality implemented by the system itself, by changing the content of the configuration memory. Designing safety-critical applications requires accurate methodologies to evaluate the system’s sensitivity to SEUs as early as possible during the design process. Moreover it is necessary to detect the occurrence of SEUs during the system life-time. To this purpose test patterns should be generated during the design process, and then applied to the inputs of the system during its operation. In this thesis we propose a set of software tools that could be used by designers of SRAM-based FPGA safety-critical applications to assess the sensitivity to SEUs of the system and to generate test patterns for in-service testing. The main feature of these tools is that they implement a model of SEUs affecting the configuration bits controlling the logic and routing resources of an FPGA device that has been demonstrated to be much more accurate than the classical stuck-at and open/short models, that are commonly used in the analysis of faults in digital devices. By keeping this accurate fault model into account, the proposed tools are more accurate than similar academic and commercial tools today available for the analysis of faults in digital circuits, that do not take into account the features of the FPGA technology.. In particular three tools have been designed and developed: (i) ASSESS: Accurate Simulator of SEuS affecting the configuration memory of SRAM-based FPGAs, a simulator of SEUs affecting the configuration memory of an SRAM-based FPGA system for the early assessment of the sensitivity to SEUs; (ii) UA2TPG: Untestability Analyzer and Automatic Test Pattern Generator for SEUs Affecting the Configuration Memory of SRAM-based FPGAs, a static analysis tool for the identification of the untestable SEUs and for the automatic generation of test patterns for in-service testing of the 100% of the testable SEUs; and (iii) GABES: Genetic Algorithm Based Environment for SEU Testing in SRAM-FPGAs, a Genetic Algorithm-based Environment for the generation of an optimized set of test patterns for in-service testing of SEUs. The proposed tools have been applied to some circuits from the ITC’99 benchmark. The results obtained from these experiments have been compared with results obtained by similar experiments in which we considered the stuck-at fault model, instead of the more accurate model for SEUs. From the comparison of these experiments we have been able to verify that the proposed software tools are actually more accurate than similar tools today available. In particular the comparison between results obtained using ASSESS with those obtained by fault injection has shown that the proposed fault simulator has an average error of 0:1% and a maximum error of 0:5%, while using a stuck-at fault simulator the average error with respect of the fault injection experiment has been 15:1% with a maximum error of 56:2%. Similarly the comparison between the results obtained using UA2TPG for the accurate SEU model, with the results obtained for stuck-at faults has shown an average difference of untestability of 7:9% with a maximum of 37:4%. Finally the comparison between fault coverages obtained by test patterns generated for the accurate model of SEUs and the fault coverages obtained by test pattern designed for stuck-at faults, shows that the former detect the 100% of the testable faults, while the latter reach an average fault coverage of 78:9%, with a minimum of 54% and a maximum of 93:16%

A configurable board-level adaptive incremental diagnosis technique based on decision trees

Functional diagnosis for complex electronic boards is a time-consuming task that requires big expertise to the diagnosis engineers. In this paper we propose a new engine for board-level adaptive incremental functional diagnosis based on decision trees. The engine incrementally selects the tests that have to be executed and based on the test outcomes it automatically stops the diagnosis as soon as one or more faulty candidates can be identified, thus allowing to reduce the number of executed tests. Moreover, we propose a configurable early stop condition for the engine that allows to further reduce the number of executed tests leveraging the diagnosis accuracy. The effectiveness of the proposed approach has been assessed using a set of synthetic but realistic boards and three industrial boards

UA2TPG: An untestability analyzer and test pattern generator for SEUs in the configuration memory of SRAM-based FPGAs

This paper presents UA2TPG, a static analysis tool for the untestability proof and automatic test pattern generation for SEUs in the configuration memory of SRAM-based FPGA systems. The tool is based on the model-checking verification technique. An accurate fault model for both logic components and routing structures is adopted. Experimental results show that many circuits have a significant number of untestable faults, and their detection enables more efficient test pattern generation and on-line testing. The tool is mainly intended to support on-line testing of critical components in FPGA fault-tolerant systems

Spectral enclosures for the damped elastic wave equation

In this paper we investigate spectral properties of the damped elastic wave equation. Deducing a correspondence between the eigenvalue problem of this model and the one of Lamé operators with non self-adjoint perturbations, we provide quantitative bounds on the location of the point spectrum in terms of suitable norms of the damping coefficient

Palmitoylethanolamide dampens reactive astrogliosis and improves neuronal trophic support in a triple transgenic model of Alzheimer’s disease: in vitro and in vivo evidence

Alzheimer’s disease (AD) is a neurodegenerative disorder responsible for the majority of dementia cases in elderly people. It is widely accepted that the main hallmarks of AD are not only senile plaques and neurofibrillary tangles but also reactive astrogliosis, which often precedes detrimental deposits and neuronal atrophy. Such phenomenon facilitates the regeneration of neural networks; however, under some circumstances, like in AD, reactive astrogliosis is detrimental, depriving neurons of the homeostatic support, thus contributing to neuronal loss. We investigated the presence of reactive astrogliosis in 3×Tg-AD mice and the effects of palmitoylethanolamide (PEA), a well-documented anti-inflammatory molecule, by in vitro and in vivo studies. In vitro results revealed a basal reactive state in primary cortical 3×Tg-AD-derived astrocytes and the ability of PEA to counteract such phenomenon and improve viability of 3×Tg-AD-derived neurons. In vivo observations, performed using ultramicronized- (um-) PEA, a formulation endowed with best bioavailability, confirmed the efficacy of this compound. Moreover, the schedule of treatment, mimicking the clinic use (chronic daily administration), revealed its beneficial pharmacological properties in dampening reactive astrogliosis and promoting the glial neurosupportive function. Collectively, our results encourage further investigation on PEA effects, suggesting it as an alternative or adjunct treatment approach for innovative AD therapy

Unique Continuation Properties from one time for hyperbolic Schr\"odinger equations

In this paper, we investigate properties of unique continuation for hyperbolic Schr\"odinger equations with time-dependent complex-valued electric fields and time-independent real magnetic fields. We show that positive masses inside of a bounded region at a single time propagate outside the region and prove gaussian lower bounds for the solutions, provided a suitable average in space-time cylinders is taken.Comment: arXiv admin note: substantial text overlap with arXiv:2107.1078

Optimizing the Use of Behavioral Locking for High-Level Synthesis

The globalization of the electronics supply chain requires effective methods to thwart reverse engineering and IP theft. Logic locking is a promising solution, but there are many open concerns. First, even when applied at a higher level of abstraction, locking may result in significant overhead without improving the security metric. Second, optimizing a security metric is application-dependent and designers must evaluate and compare alternative solutions. We propose a meta-framework to optimize the use of behavioral locking during the high-level synthesis (HLS) of IP cores. Our method operates on chip's specification (before HLS) and it is compatible with all HLS tools, complementing industrial EDA flows. Our meta-framework supports different strategies to explore the design space and to select points to be locked automatically. We evaluated our method on the optimization of differential entropy, achieving better results than random or topological locking: 1) we always identify a valid solution that optimizes the security metric, while topological and random locking can generate unfeasible solutions; 2) we minimize the number of bits used for locking up to more than 90% (requiring smaller tamper-proof memories); 3) we make better use of hardware resources since we obtain similar overheads but with higher security metric.Comment: Accepted for publication in IEEE Transactions on Computer-Aided Design of Integrated Circuits and System

SAFETY AND HEALTH SITE INSPECTIONS FOR ON-FIELD RISK ANALYSIS AND TRAINING

The field of construction is always affected by a large number of accidents at work that have many different causes and responsible. Therefore, it is of utmost importance to focus on all these issues, in order to reduce all risk factors that can undermine individuals’ safety on building sites. The objective of the research is then the development of a method for quick on site analysis of all critical issues that can create accidents and identification of the related causes in order to directly provide a correct and focused training identified as the best method to act on the causes to reduce accidents. The research was carried on during construction of the Universal Exhibition of Milan – Expo 2015 – that counted almost 70 contemporary construction sites. To reach the goals further research steps has been followed and in particular: (i) inspections on building sites through all the Expo area; (ii) analysis of the main identified problems; (iii) development of a methodology to quickly identify the cause of problems; (iv) validation of the method through back office analysis of site documents; (v) correct on-site training according to found problem. During the whole construction site, the improvements in criticalities solving have been visible thanks to the focused training. The developed method, carried on in a high-risk environment, is applicable in any other building sites and environment as independent from the boundary conditions of the place

Lightweight protection of cryptographic hardware accelerators against differential fault analysis

© 2020 IEEE. Personal use of this material is permitted. Permission from IEEE must be obtained for all other uses, in any current or future media, including reprinting/republishing this material for advertising or promotional purposes,creating new collective works, for resale or redistribution to servers or lists, or reuse of any copyrighted component of this work in other works.Hardware acceleration circuits for cryptographic algorithms are largely deployed in a wide range of products. The HW implementations of such algorithms often suffer from a number of vulnerabilities that expose systems to several attacks, e.g., differential fault analysis (DFA). The challenge for designers is to protect cryptographic accelerators in a cost-effective and power-efficient way. In this paper, we propose a lightweight technique for protecting hardware accelerators implementing AES and SHA-2 (which are two widely used NIST standards) against DFA. The proposed technique exploits partial redundancy to first detect the occurrence of a fault and then to react to the attack by obfuscating the output values. An experimental campaign demonstrated that the overhead introduced is 8.32% for AES and 3.88% for SHA-2 in terms of area, 0.81% for AES and 12.31% for SHA-2 in terms of power with no working frequency reduction. Moreover, a comparative analysis showed that our proposal outperforms the most recent related countermeasures.Peer ReviewedPostprint (author's final draft